1. Technical Field
The following relates generally to power saving for integrated circuits, and more specifically to a method and apparatus for clock power saving in multiport latch arrays.
2. Background
In semiconductor design, standard cell methodology is an approach of designing integrated circuits (ICs) such as application-specific integrated circuits (ASICs) using abstract logic representations to create low-level, very-large-scale integration (VLSI) layouts. Each abstract logic representation is implemented with a group of transistor and interconnect structures as a standard cell. For example, Boolean logic functions such as AND, OR, XOR, XNOR, and NOR functions may be implemented using standard cells. In addition to these basic Boolean logic functions, more complex logic functions may be implemented as standard cells, as well as storage functions such as flip-flop or latch storage cells.
Standard cells makes it possible for one designer to focus on high-level aspects of digital design, such as creating various results using logic functions, while another designer may focus on specific aspects of implementation, such as circuit layout and optimization. Standard cell methodology, along with constant improvements in semiconductor manufacturing techniques, has provided chip designers with the ability to scale ASICs from comparatively simple, single-function ICs implemented with several thousand gates to complex, multi-million-plus gate system-on-a-chip (SoC) devices.
Regardless of design complexity, logic circuits require a timing source to operate. Typically, a clock circuit may be used to generate timing signals that are distributed to all devices in the logic circuit over a timing source distribution network referred to as a clock net. The timing signal is composed of a signal that consists of alternating ones and zeros, generated by a switching of the clock circuit. The clock circuit must drive the timing signal over the clock net, which means the clock circuit must constantly change the state of the timing signal from ones-to-zeros, and zeros-to-ones by charging and discharging the clock net, respectively The cycling of charging/discharging operations requires expenditure of power referred to as clock switching power, and clock switching power is one of the major power dissipation sources in all ASIC implementations because a clock circuit is constantly running.
The amount of power expended to cycle, or charge/discharge, a clock net is proportional to a resistance of the clock net to change, as well as a frequency of the charge/discharge cycle, as shown in the following formula:Power=CV2 f,where C is a load capacitance of the clock net, V is the voltage to charge the load capacitance, and f is the operational frequency of the clock net. Thus, one component of the change resistance of the clock net is due to the capacitance of the clock net, which includes coupling capacitance. Each device that is coupled to the clock net contributes to coupling capacitance. Increased coupling capacitance of the clock net will result in an increase in clock switching power consumption. Conversely, decreasing coupling capacitance of the clock net will result in a decrease of the clock switching power. Because operating frequencies for devices are only likely to increase in newer designs, and the voltage levels at which these devices may be operated are unlikely to be reduced much further for the immediate future, the ability to decrease coupling capacitance in the clock net is becoming critical in improving clock switching efficiency.
In the case of designs utilizing standard cells, a change in efficiency for a particular standard cell may have a multiplied impact because the particular standard cell may be used numerous times. Therefore, it would desirable to improve the efficiency of the design of standard cells as well as any circuit elements therein.
In accordance with common practice, some of the drawings may be simplified for clarity. Thus, the drawings may not depict all of the elements of a given apparatus (e.g., device) or method. Finally, like reference numerals may be used to denote like features throughout the specification and figures.